1. Field of Invention
The present invention relates to a memory cell and a manufacturing method thereof, and particularly to a DRAM (dynamic random access memory) cell utilizing floating body effect (FBE) and a manufacturing method thereof, which belongs to semiconductor manufacturing field.
2. Description of Related Arts
With development of the ULSI (Ultra Large Scale Integration), processing unit, memory cell, analog circuit, logical interface, and even RF circuit are integrated into a single chip, forming a so called SoC (System on Chip). As important parts of SoC, embedded memory and logic circuit are integrated into a single chip, which takes more than 50% of the microprocessor or system chip area, and may take more area according the application requirement. The feature size of CMOS will continue to scale down to less than 40 nm according to Moore's law. The conventional embedded DRAM (eDRAM) is facing more and more difficulties in scaling down the feature size. Each memory cell of the conventional eDRAM includes a transistor and a capacitor (1T1C, one-transistor one-capacitor). It is very complicated to prepare stack capacitor by adopting high k material or prepare trench capacitor of high aspect ratio during the IC manufacturing process. The height of the memory unit is much larger than the width due to the structure of the trench capacitor (the ratio of height to width is over 30:1). Therefore the manufacturing process is very complicated and is not compatible with conventional CMOS ULSI manufacturing process. Therefore, the application of the eDRAM to SoC is limited.
In recent years, attention is paid to a kind of DRAM utilizing floating body effect. It removes the capacitor in the conventional DRAM, and takes isolated floating body as a storage node to write “1” and “0” by utilizing the floating body effect caused by the buried oxide layer (BOX) in the silicon on insulator (SOI). As shown in FIG. 1, the carries (holes) are gathered in the floating body, which is defined as a first storage status “1”. As shown in FIG. 2, because the PN junction is positive biased, the carries (holes) are emitted out from the floating body, which is defined as a second storage status “0”. Detecting the threshold voltage difference caused by the two statuses via current can realize the read operation. This kind of floating body cell (FBC) can constitute memory of high density, and has lower cost and simpler manufacturing process. The area of FBC is 3 to 5 times smaller than that of the SRAM. Therefore the conventional DRAM will be replaced by the FBC. It is reported that the floating body cell is one-transistor floating body (1T/FB) based on SOI. S. Okhonin et al. disclose such DRAM cell in A Capacitor-less/T-DRAM Cell of IEEE Electron Device Letters Vol. 23, No. 2 (February 2002), and T. Ohsawa et al. also disclose such DRAM cell in Memory Design Using One-Transistor Gain Cell on SOI of IEEE International Solid-State Circuits Conference (February 2002). FIG. 3 is a sectional view of a 1T/FB DRAM cell. The DRAM cell 100 includes a silicon substrate 101, a buried oxide layer 102, oxidation regions 103 and 104, N++ type source region 105, N++ type drain region 106, N+ type source region 107, N+ type drain region 108, P type floating body 109, gate oxidation region 110, gate electrode 111, side walls 112 and 113. The floating body 109 is to store charges so as to adjust the threshold voltage VT of the DRAM cell. The N++ type source region 105 is usually grounded. When write “1” to the DRAM cell, apply a high voltage to the N++ type drain region 106 and apply a medium voltage to the gate electrode 111 to produce a relative high electric field in the N++ type drain region 106. The channel electrons in the high electric field of the N++ type drain region 106 obtain enough energy to produce electron-hole pairs via collision. The holes move to the floating body with lower electric potential. Due to a barrier existing in the source-body junction, the holes will gather in the floating body to raise the electric potential of the floating body. Due to the body effect, when the voltage of the P type substrate rises, the threshold voltage falls, which is equivalent to an operation of writing “1”. In order to write “0” to the DRAM cell, apply negative voltage to the N++ type drain region 106 and apply medium voltage to the gate electrode 111. The electric potential of the substrate is positive due to the holes existing in the floating body, which causes the positive bias of the substrate-drain region PN junction. Then the holes in the floating body move to the drain region 106, so that the voltage of the substrate falls so as to raise the threshold voltage, which is equivalent to the operation of writing “0”.
During the reading operation, apply medium voltage to the drain region 106 and the gate electrode 111, and ground the source region. When the stored data is “1”, a relative large current flow through the source and drain region, and when the stored data is “1”, a relative small current flows through the source and drain region, so that the data stored in the DRAM cell can be determined by comparing the current flowing through the source and drain region to the reference current. The gate electrode of the unchecked DRAM cell in the array contacts to the negative voltage to lower the leakage current and malfunction rate.
The 1T/FB memory cell reduces the area, which is only 4 to 7 F2 (F means feature size), so that the integration of the memory cell is largely improved. The drawback of this memory cell is that the circuit and logic design is complicated and the leakage current is hardly controlled.
In order to further reduce the area of the memory cell, and lower the leakage current, the present invention provides a highly efficient DRAM cell utilizing floating body effect, which has low power consumption, has simple manufacturing process, and is compatible to the conventional CMOS and conventional logic circuit manufacturing process.